Ashbin Shiju

Designed and verified RTL hardware modules for cache coherence, memory consistency, and AMBA ACE/TileLink protocols. Analyzed RocketChip SoC architecture and validated dual-core cache coherence using bare-metal RISC-V programs in Chipyard. Replaced AMBA ACE with TileLink in the AS1061 processor and verified TRI protocol functionality in the AS1161 processor, covering cache requests, responses, invalidations, and flush operations.

During my internship, I gained knowledge of computer architecture, branch prediction in RISC V processors, and the implementation of an advanced branch  predictor called GShare predictor using Hardware Description Language Verilog. I also researched and began the implementation of a modern branch predictor called TAGE.

Worked on project of implementing a security wrapper module in router of NoC

I gained knowledge in connecting various sensors, such as the DHT11, to microcontrollers, such as the Arduino and esp8266, during my internship.