Kiran Kariyannavar

Developed following digital IPs (reuse factor from existing IPs) : Clock/Reset controller(40%), FRO recalibration(40%), XTAL controller (0%), AHB compliant RRAM cache controller(0%) IP requirements and micro architecture documentation in Oxygen in Dita format RTL implementation & verification for secure automotive SoCs Spyglass Lint/CDC/DFT checks Firmware support with bitfield scripts Exposure to Matlab system simulations IC level C based directed testcase development and verification

DfT RTL implementation, scan insertion, ATPG (Stuck-at, Transition, Path Delay) Mixed-signal test integration (CTAG.AMS) Memory BIST Silicon bring-up & test optimization

Verification of automotive SoCs (GPIO, SPI, PLL) Memory Test Chip for Memory Characterization Scan insertion, LBIST, Boundary Scan for Texas Instruments Houston & NEC Japan projects

Master Thesis Project: Connecting the human body - Models, Connections and Competition; Working prototype was demonstrated at •20th European Conference on Circuit Theory and Design (ECCTD2011) •Ericsson keynote @ CES2012 Mixed Signal Project 1: Design of First-Order Sigma-Delta Modulator with 3-bit

FPGA implementation of counter mode twofish cipher