Ayoub Seddik

Angestellt, Pr. FPGA Engineer, Rockwell Collins Deutschland GmbH, a part of Collins Aerospace

Heidelberg, Deutschland

Fähigkeiten und Kenntnisse

FPGA-Entwicklung
FPGA verification
VHDL
DO-254
C/C++
TCL
Xilinx
Microsemi
Vivado
ISE
DOORS
NIOSII
Modelsim
Questasim
Eagle
Microwind
Altium Designer
Bus CAN
DDR3
Serial Flash NOR
SPI
Arinc
RS232...
JTAG
IPs and FPGAs design and development
Specification and architecture documents elaborati
FPGA-Programmierung
CDC
C++
Python

Werdegang

Berufserfahrung von Ayoub Seddik

  • Bis heute 8 Jahre und 7 Monate, seit Okt. 2015

    Pr. FPGA Engineer

    Rockwell Collins Deutschland GmbH, a part of Collins Aerospace

    FPGA design, integration and verification (front-end/back-end) for airborne electronic hardware.

  • 4 Jahre und 4 Monate, Juli 2011 - Okt. 2015

    Hardware Engineer

    HCELL-engineering

    Design and verification of embedded systems for airborne electronic hardware according to the assurance guidance RTCA DO254.

  • 6 Monate, Feb. 2011 - Juli 2011

    Final Year Project

    Altronic

    -Design and development in VHDL of an OFDM IP for LTE channel. -Environment: Altium Designer, Nanoboard3000, FPGA Xilinx, VHDL.

  • 2 Monate, Juni 2010 - Juli 2010

    Engineer internship

    LEONI AG

    With the MMC team (Module Manufacturing Center), the project consists of the design of a test board for the manufactured modules.

  • 3 Monate, Juni 2009 - Aug. 2009

    First internship

    CIV-Tunisia

    Within the test department, the objective was to participate to the manufactured PCB test activities

Ausbildung von Ayoub Seddik

  • 2 Jahre und 10 Monate, Sep. 2008 - Juni 2011

    Electronics

    ENISo

    Electronics systems desing

Sprachen

  • Englisch

    Fließend

  • Französisch

    Fließend

  • Deutsch

    Fließend

  • Arabisch

    Fließend

Interessen

Travel
cinema
History

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