Cicero Chang

Angestellt, Senior Manager, Powerchip Semiconductor Manufacturing Corporation
Taipei, Taiwan

Skills

Marketing
Key Account Management
Business Development
Management
Project Management
Account Management
Engineering
Test method
Product Development
English Language
German
Key Account
Team work
Professional experience
Responsible
Leadership
Problem Solving
Communication skills
Technical Knowledge
Analytical skills

Timeline

Professional experience for Cicero Chang

  • Current 9 years and 4 months, since Apr 2016

    Senior Manager

    Powerchip Semiconductor Manufacturing Corporation

    1. Lead customer engineering service team for Tier1 US/Japan/Germany customer on IGBT/PMIC/Discrete/MCU segments 2. Problem solving and achieve the goal with the team 3. Regular update key project status to the general manager of foundry business unit

  • 1 year and 3 months, Apr 2014 - Jun 2015

    Foundry Project Manager

    Goertek

    1. Foundry management of TSMC and GlobalFoundries for MEMS microphone project, to drive yield improvement and cowork with RD team for new product development 2. Product tape-out and purchase order management, lot delivery schedule control

  • 5 years and 3 months, Apr 2008 - Jun 2013

    Deputy Manager, Customer Engineering Service

    Maxchip Electronics Corporation

    Best known employee (BKE) in 2010 Customer engineering service 1. Tier1 US/Japan/Korean customer (PMIC/CMOS/LCDD/NOR Flash), 90nm to 180nm node 2. Customer project management, product tape-out, engineering meeting, customer visit and QBR handling 3. Timely escalate customer key issue to management Technical marketing: 1. MCU/CIS new customer engagement, contract and project management, market analysis 2. Technology roadmap arrangement, and revenues/tape-out analysis by product segments

  • 7 months, Apr 2007 - Oct 2007

    Senior Device Engineer

    TSMC

    1. Backend Advanced Technology Project (3D IC), through silicon via (TSV) development 2. Verification of TSV process impact on electrical properties of device 3. Testkey design for TSV process

  • 4 years and 10 months, Jul 2002 - Apr 2007

    Principle Device Engineer

    UMC

    1. 0.15um and 90nm node testkey design, tape-out handling 2. Device charateristic and failure analysis 3. Tester and program maintainence (HP-Basic/C)

Languages

  • Chinese

    First language

  • German

    Basic

  • English

    Fluent

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