Evgeny Kuxa

Created layouts for device test-cells and analog validation circuits in Cadence Virtuoso. Developed compact models for RF devices in SOI UltraCMOS processes. Conducted reliability testing and large-signal, harmonic load-pull, characterisation for CMOS devices, targeted for power amplifier applications. Provided noise-enabled nonlinear PIN diode model thus allowing accurate LNA simulations Designed and executed test plans for small-signal device characterisation.

Built RF front-end chains for counter-UAV systems. Procured high-reliability RF components, ensuring compliance with quality control standards. Validated designs in lab environment and assisted with EMC test preparation.

Design and simulation of efficient RF power amplifiers for 5G MIMO base stations Layout of RF PCB modules and their full 3D simulations Load-Pull measurements of candidate devices using active MT2000 system

Microwave IC design and compound semiconductor (GaAs, GaN) device modelling Layout of transistor test cells for MPW runs, including calibration and de-embedding structures On-wafer device and circuit measurements

• Deliver lectures, conduct tutorial and laboratory sessions on electronics engineering subjects for Undergraduate and Master students, mark reports and assignments, provide consultations. • Was selected 2 times to convene postgraduate units; multiple times acted as a head tutor liaising between the tutors and unit conveners. • Received good feedback from the students through anonymous surveys. • Completed the Tutoring Induction Program for teaching skills development.

• Designed and simulated for tapeout, a low-power Ka-band (40 GHz) GaAs amplifier using a low-noise 0.1 µm pHEMT process from WIN Semiconductors. • Designed a Ka-band SiGe oscillator in a 0.13 µm BiCMOS process (IHP) for a novel compact passive resonator structure testing. Experience in Balun and Passive Filter design in SiGe CMOS process. • Use AWR Design Environment for schematic capture, chip routing and simulations. Use AXIEM for electromagnetic simulations. Verify my designs using DRC and LVS checks.

Maintained the process of dielectric chemical vapor deposition in a SOI CMOS manufacturing foundry. • Developed an advanced deposition technique to decreasing latencies in the conducting lines due to parasitic capacitance. • Programmed the tool's deposition sequences, editing steps and choosing process parameters (RF power, step time, reactant flow rate). • Participated in the tool's maintenance procedures.. • Operated the tool from clean room.

Radio Frequency Integrated Circuit Design, High-Performance Compound-Semiconductor Manufacturing Process Characterization

Digital Communication Systems, Wireless Systems, Broadband Wireless Networks

Solid-State Electronics, Semiconductor Physics, Theory of Circuits, RF Devices