Mina Abdallah

Angestellt, RFIC Design Engineer, Apple
Unterhaching, Germany

Fähigkeiten und Kenntnisse

PLL
RFIC
Analog
Cadence-Virtuoso
Verilog-AMS
Verilog VHDL
Matlab
Octave-GNU
C++
Cppsim
system-c/system-c-ams
Wireless Communication
wire-line Communication
WiFi
BT
BLE
GSM
LTE
Lab testing

Werdegang

Berufserfahrung von Mina Abdallah

  • Current 6 years and 7 months, since Nov 2019

    RFIC Design Engineer

    Apple

  • 3 years and 7 months, Apr 2016 - Oct 2019

    Senior RF circuit design Transceiver

    Intel Deutschland GmbH
  • 1 year and 7 months, Sep 2014 - Mar 2016

    Senior RFIC Design Engineer

    Atmel Corporation

    • Fractional-N PLL design (For connectivity applications: 802.11 a/b/g/n/ac, Bluetooth, FM radio, Clock generation): --> • System/Architectural design, --> • Noise budgeting, --> • Circuit development --> • EM simulations --> • Cross-talk investigation --> • Lab measurements and testing automation • Traveling between different sites in the US and Egypt • Managerial rule: --> • Leading junior team members in macro definition and design.

  • 1 year, Sep 2013 - Aug 2014

    Senior RFIC Design Engineer

    Newport Media inc. Acquired by ATMEL corporation August 2014

    • Fractional-N PLL design (For connectivity applications: 802.11 a/b/g/n/ac, Bluetooth, FM radio, Clock generation): --> • System/Architectural design, --> • Noise budgeting, --> • Circuit development --> • EM simulations --> • Cross-talk investigation • Managerial rule: --> • Leading junior team members in macro definition and design.

  • 6 months, Apr 2013 - Sep 2013

    Analog Design Engineer

    Intel Corporation

    • Design oscillators for 2G/3G application

  • 2 years and 2 months, Mar 2011 - Apr 2013

    Analog Design Engineer

    Intel Corporation

    • Receiver design: System level architecture For 2G/2.5G. • Calibration loop definition. • Control and sequencing definition. • Local oscillator design: Phase noise level planning, Micro specification definition. For 2G. • Transmitter design: Micro specification definition. For 2G • Managerial rule: --> • Leading small teams in macros definition and design. • Traveling between different sites in Egypt and Germany/Austria to provide a communication link. • Circuit development For 2G/3G/LTE:

  • 2 years and 8 months, Aug 2008 - Mar 2011

    Analog Design Engineer

    SySDSoft (Acquired by Intel Mobile Communications on March 2011)

    • Frequency synthesizer design: system design and architecture, Micro specification definition. For Wi-Fi/Wi-Max/ZigBee • DC offset cancellation loops definition and implementation. • Circuit development: (VCOs, Phase detectors, Frequency dividers, current DAC, Serializer, switched PA).

Ausbildung von Mina Abdallah

  • 5 years and 5 months, Oct 2008 - Feb 2014

    Electronic Engineering

    Cairo University

    Mixed-signal IC design (AD-PLL, CDRs)

  • 4 years and 11 months, Sep 2003 - Jul 2008

    Electronic Engineering

    Cairo University

Sprachen

  • English

    C1 (Fließend)

  • Arabic

    C2 (Verhandlungssicher / Muttersprachlich)

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