Ganesh Pagadala

o Experienced in HDK validation of INTEL & TSMC process which includes TFM, cell library and PDK to improve design efficiency and IP handoff. o Estimated PPA on various technology nodes using analog designs. o Evaluated analog layout TFM functionality for different process, participated in full-chip integration and develop automation scripts in SKILL. o Lead performance bench marking of analog & digital flows and work with internal/external EDA vendors to deploy solutions in project environment.

Product Development Engineer, Client Location at Intel and Cypress Semiconductor. o Experience indifferent generations of FinFET included 10nm and22nm. o Expertise in handling TAPE-OUT closure activities in the chip level integration. o Provided Analog Layout Training for fresh graduates who joined the team. o Awarded as EXECUTION MINDSET(Client Comforter) from country head.

o Experienced in 2D(NAND),3D-Memory(BiCS) sub blocks layout design Including like Charge Pumps (VMSYS),Digital Temperature Co-efficient (DTCO) , Word Line Leakage Detection (WLLD), YLOG(SERDES),Voltage Generators (VOLGEN), Power Amplifier(PWON),Clock Generator (CLKGEN),IO Pads and ESD’s. o Effectively involved in the Standard cells & Macro cells library development of various generations. o Mentored Resources as a BLOCK LEAD and Explored different process Automation Techniques and addressed the team.

o Focused on sub micron technology nodes like1 30nm, 90nm, 45nm, 28nm and process included TSMC,GF. o Designed layouts for Digital/Analog/Mixed/RF sub blocks including Standard Cells,Level Shifter,OP-AMP,BGR,DAC and PLL. o Acquired knowledge on PCELL creation and Analog/RF Layout Techniques like Matching,Shielding, parasitic optimization and Noise Isolation.

Main Emphasis – V L S I , Analog and Digital Electronics,circuit thoery,Antennas, Microwave,signals and systems,Control Systems,Communications.