Gonzalo Federico Cuñarro Podesta

• Delivered silicon-ready full-chip integration and DRC/LVS-clean sign-off in 22 nm FD-SOI and 28 nm for FeFET non-volatile memory, under tight deadlines. • Owned the Cadence Virtuoso EDA environment and implemented server-side design-data management (Cliosoft SOS) for version control and project integrity. • Supported verification and modelling of memory blocks in SystemVerilog and Verilog-A.

Ayudante de diseño de circuitos analógicos y pcb