Guerkan Ilicali

System Architect, Power Rectifiers

Process & device integration HVCMOS technology for automotive products. Introduction and qualification of new process modules and devices. Design rule definition based on statistical process variations and tolerances. Electrical parameter specifications. Test structure development. Wafer level reliability. Planning, coordination and analysis of fab experiments. Excel-VBA-Tool development for data analysis. Yield engineering support. Development and integration. Continuous improvement, Zero ppm.

• Technical managerial position supervising R&D team of 10 employees. Responsible for deploying employees for particular tasks according to their skill sets and optimize resource utilization. • Technical foundry support. • Lead role in technology development for Smart Power Integration - 0.35um high voltage BCD MOS technology • Coordination and implementation of technology development relevant quality assurance policies, specifications and technical documentation. Intern/Extern Audit-compliance.

• Process Integration. Definition of unit process specifications based on statistical process control. • Device Design & Library. Introduction of novel devices into design flow. • Test structure development and layout. Definition of electrical parameter specifications based on statistical analysis. • Wafer Level Reliability • Lot & personnel supervision. Split lot plans, experimental runs, fab run-card optimizations. • Design Manual, FMEA, Relevant quality assurance documentation.

Design Technology Interface - Product Development- • Electrical device characterization and compact modeling for 90, 65 and 46nm technology nodes. • Model-to-Hardware correlation, parameter extraction & model development. • Design Manual support and Layout Rules. • Implementation of layout dependencies into design flow (STI Stress, well proximity, device matching etc.). • Test structure development and layout definition for sub-micron effects. • MS Excel-Tool development for parameter extraction.

Corporate Research, Nano Devices Laboratories. • Realization of sub-50nm Planar Single and Double Gate SOI CMOS Devices. • Device design, device simulation and process integration. • Layer transfer (fusion wafer bonding) for fabrication of planar Double Gate transistors. • Lot supervision, planning, coordination and analysis of experiments.

Corporate Logic - Department of Technology Innovation- • Technology pre-development for sub-100nm technology nodes. • CMOS process integration, particularly transistor gate stack, FEOL (Front-End-of-Line), high-K gate dielectrics and metal gates • Oxynitrides with Atomic Layer Deposition (ALD) for CMOS gate stack.

Device design and simulation (TCAD), Process Integration, Wafer Bonding. Dissertation: Design and fabrication of planar double gate SOI transistors with wafer fusion bonding.

Quantum Physics, Solid State Theory and semiconductor physics. Master project in Solid state electonics entitled " Zirconium dioxide thin films as a high-K gate dielectric for future CMOS technologies"

Quantum pyhsics, atomic&molecular physics, Solid state theory. Graduation Thesis: Introduction to computer simulation techniques in physics