Gürol Sağlam

Temporary assignment at TESAT (Aug 2026 - Present) • Analysis of device and system requirements for optimal selection of system partitioning, architectures, and components • Development, verification, and commissioning of highly complex SoC FPGAs for DSP or high-bit-rate network applications • Active support of the HW/SW co-design approach • Agile verification using evaluation boards in interaction with software development • Documentation of the work performed in accordance with space industry requirements

• Conducted research on digital logic design for Printed Electronics usng Synopsys and ModelSim • Actualized and optimized hardware for machine learning (ML) models, addressing PE constraints • Performed verification and Static Timing Analysis (STA) following the ASIC Design Flow • Delivered automated Python frameworks, training MLPs for bespoke approximate digital designs and approximating ALUs with a genetic algorithm • Built a Python RISCV Assembly Generator for MLPs, reducing memory usage and branches

• Executed in-depth research on SoC/FPGA design utilizing Quartus Prime and ModelSim • Designed RTL for DCO-OFDM, enhancing high-bandwidth communication in the Visible Light Spectrum • Provided tools for auto-generating parameterizable designs, streamlining the design process • Carried out rigorous debugging on real hardware, identifying and resolving hardware-related issues to ensure optimal performance and functionality