Dr. Angel José Soto

Angestellt, Senior Staff Digital Design Engineer, INDI
Dresden, Germany

Fähigkeiten und Kenntnisse

Power electronics
asic
VHDL
CAD
Synopsys EDA
Cadence
xilixs vivado
FPGA Design
ASIC PLD FPGA Digital Logic Design
System Verilog
UVM
Mixed-Signal
Mentor Graphics
Automotive
Linux

Werdegang

Berufserfahrung von Angel José Soto

  • Current 3 years and 5 months, since Jan 2023

    Senior Staff Digital Design Engineer

    INDI

  • Current 6 years and 11 months, since Jul 2019

    Digital Mixed Signal Design

    DMOS GmbH

    Mixed-Signal Design and Simulation for speeding up the development of ASICs and ASSP for the automotive industry.

  • 1 year and 1 month, Jun 2018 - Jun 2019

    Digital Design Engineer

    DMOS GmbH

    Using digital design approach for mixed-signal automotive and industrial ASIC design.

  • 3 years, Jun 2015 - May 2018

    R&D Engineer

    CONICET

    ASIC and FPGA designs. The design of analogue, digital or mixed-signal ASICs in several processes depending on the requirements of the researchers. Further the design and implementation of digital parts in Xilinx's FPGA platforms for the test of ASIC and new digital processing architectures.

  • 3 months, Aug 2017 - Oct 2017

    Invited R&D Engineer

    Fermilab

    Definition and implementation of firmware and software architecture for a new CCD acquisition system.

  • 2 months, Feb 2017 - Mar 2017

    Invited R&D Engineer

    Fermilab

    Collaboration in the architecture and firmware design of a new acquisition system for CCD sensors were the main objectives. The networking and the future work definition were the "key" factor of the stage.

Ausbildung von Angel José Soto

  • 5 years, Apr 2010 - Mar 2015

    PhD Engineering

    Universidad Nacional del Sur

    – Development of SIMO (single inductor multiple outputs) Fully integrated converter in 65nm process. – High power converter with magnetic LTCC (low-temperature co-fired ceramics) coupled inductor filter. – Hands-on lab measurement and practical validation.

  • 7 years and 6 months, Mar 2002 - Aug 2009

    Electronics Engineering

    Universidad Nacional del Sur

    Development of ASIC for Isolated Power Inverter in ON05 process.

Sprachen

  • Spanish

    C2 (Verhandlungssicher / Muttersprachlich)

  • English

    C1 (Fließend)

  • German

    A1-A2 (Grundkenntnisse)

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