Jiewei Chen
Skills
Timeline
Professional experience for Jiewei Chen
- Current 4 years and 9 months, since Oct 2021
Sr. Process Integration Engineer
Micron Technology, Inc.
170s 3D RG NAND Staircase Contact Module Owner
- 2 years and 7 months, Apr 2019 - Oct 2021
Engineer - R&D NAND Process IntegrationEngineer
Micron Technology, Inc.
150s 3D RG NAND Replacement Gate Module Owner
- 3 months, Jul 2018 - Sep 2018
Intern, Wet Process Non-Volatile Memory
Micron Technology, Inc.
Designed and performed fundamental electrochemistry research to optimize wet process flow for source corrosion issue
Educational background for Jiewei Chen
- 2 years and 2 months, Oct 2016 - Nov 2018
MSc., Statistics
University of California, Davis
Grade: 3.96/4.0
- 4 years and 3 months, Oct 2014 - Dec 2018
Ph.D., Materials Science
University of California, Davis
Supervisor: Professor Alexandra Navrotsky Thesis: “Energetics and Structures of Solid Phases in Silicon - Oxygen - Carbon - Nitrogen Low-k Dielectric Materials” Full responsibility for a 4-year collaborative project with Intel Corporation, including designing and executing experiments, data analysis and scientific model validation.
- 3 years and 11 months, Sep 2010 - Jul 2014
Bachelor of Engineering (B.Eng.), Polymer Materials & Engineering
Zhejiang University
Grade: 3.83/4 Chu Kochen Honors Degree (top 5%)
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