Denis Lavaud
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Denis Lavaud
- Current 6 years and 3 months, since Mar 2020
Independent Contractor, IC Design and Verif., Indus. Software and Electronic
Freelance
IC Design and Verification, Industrial Software and Electronic Devices
- 1 year and 9 months, Jun 2018 - Feb 2020
Independent Contractor, IC Design and Verification Expert
Freelance
ASIC and FPGA Design and Verification
- 7 years and 2 months, Apr 2011 - May 2018
Technical Product Manager / Design and Verification Leader
EASii-IC
IP Product Manager / Design and Verification Manager • CoaXPress Host & Device IP technical product and functional verification manager • Technical SoC and IP project manager, multi-site teams • Design and verification methodology consultant
- 2 years and 6 months, Apr 2011 - Sep 2013
High Performance Computing Farm Manager
EASii-IC
• Creation of EASii-IC's Linux High Performance Computing Center for EDA, 150+ cores, 100+ users • Definition of network architecture and services: IBM LSF, NoMachine NX, LDAP, FlexLM, Zabbix, ...
- 1 year and 3 months, Jan 2010 - Mar 2011
Technical Consultant
Self-Employed Freelancer
• Specification of application fields of UML/SysML to semi-conductor design flows and prospect for partners • Design of analog audio products for recording studio
- 1 year, Jan 2009 - Dec 2009
Sound Engineer and Musician
Self-Employed Freelancer
· Sound engineer (music and short movie) · Composer, classical piano studies
- 2 years and 4 months, Sep 2006 - Dec 2008
Technical Product Manager, Europe
Cadence Design Systems, Inc.
C-to-Silicon Compiler, Cadence Incubation Program, Methodology Group • Product specification for seamless integration, ease of use and best performance • C to Silicon Compiler announced on July 14th, 2008
- 5 years and 9 months, Dec 2000 - Aug 2006
Application Engineer, Southern Europe
Cadence Design Systems, Inc.
Incisive Formal Verifier: • Proliferation across 3 global accounts • Success Story with ST Microelectronics, CDNlive US 2005 / EMEA 2006 HDL Analysis and Lint: • Technical product management through partnership with a global account (2001-2006) • HAL leader of the market in DVCon’04 et ’05 surveys Incisive-SystemC & Testbuilder: • Proliferation in 6 accounts in geo, plus 1 account in Sweden • Interview on ÉIH on SystemC Goals and Challenges in 2003
- 10 months, Mar 2000 - Dec 2000
Embedded Software Engineer
Thales
Real-time radar signal processing in C on a parallel multi-DSP architecture (TI C6x)
- 10 months, May 1999 - Feb 2000
ASIC Architect
SAGEM
ASIC architecture for signal processing of SDSL physical layer
- 7 months, Nov 1998 - May 1999
Embedded Software & FPGA Engineer
SAGEM
Development of interface board with a proprietary fiber network for Grenoble tramway. Altera FPGA design (VHDL) and 6810+68360 firmware programming (C, assembly)
- 1 year and 4 months, Nov 1996 - Feb 1998
Teacher
EASIEE Paris
Delivery of VHDL and 680x0 assembly language trainings
Ausbildung von Denis Lavaud
- 10 months, Oct 1996 - Jul 1997
Parallel Computer Architectures for Digital Processing
Université de Paris XI
• Processor architectures, specialized architectures, parallel languages • Image processing (INRIA Sophia Antipolis), Speech Recognition (CNRS LIMSI)
- 4 years and 11 months, Sep 1991 - Jul 1996
Micro-Electronics, Hardware Architectures and Software Development
ESIEE Paris
• Digital signal processing fundamentals • Architectures for digital procesing • ASIC, front end and back end • Final project (6 months): specification of architecture of ADSL chip-set at Philips Research Labs, Video-Communications Division
Sprachen
English
C1 (Fließend)
German
B1-B2 (Gute Kenntnisse)
Japanese
A1-A2 (Grundkenntnisse)
French
C2 (Verhandlungssicher / Muttersprachlich)
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