Mansoor Mazhar

Angestellt, ASIC contractor, Imperial
Denver, United States of America

Fähigkeiten und Kenntnisse

Circuit Design
Logic Design
Memory Design
Micro-processor Design
Layout Design
SoC Verification
Technical Lead
Silicon Debug
Mentor
Planner
Physical Design

Werdegang

Berufserfahrung von Mansoor Mazhar

  • Current 6 years and 4 months, since Feb 2020

    ASIC contractor

    Imperial

    Design of ASICs on space and space flight hardware.

  • 10 months, May 2019 - Feb 2020

    DFT/Physical Design Engineer

    Sintegra

    Design and verification of DFT circuits on an ASIC for TPU edge machine learning at Google

  • 1 year and 3 months, Feb 2018 - Apr 2019

    Sr. Design Engineer

    Teledyne

  • 1 year and 10 months, May 2016 - Feb 2018

    Circuit ASIC Design Engineer

    Lockheed Martin Corporation

  • 1 year and 5 months, Jan 2016 - May 2017

    Engineer IV

    Qualcomm

  • 9 months, May 2015 - Jan 2016

    Component Design Engineer

    Intel Corporation

  • 4 months, Jan 2015 - Apr 2015

    Physical Design Engineer IV

    Intel Corporation

  • 8 months, Jun 2014 - Jan 2015

    Physical Design Engineer

    Qualcomm Inc.

    Low power,multi voltage and multi clock Physical Design of SOC chips

  • 1 year and 8 months, Jul 2012 - Feb 2014

    Sr Electrical Engineer II

    Raytheon Company

    Physical Design and RTL Design/verification of Infra red camera chips

  • 1 year and 5 months, Feb 2011 - Jun 2012

    Physical Design Engineer

    Hewlett Packard

    Circuit,Physical and DFT Design/Verification on VLSI chips.

  • 1 year and 5 months, Oct 2009 - Feb 2011

    Memory Design Engineer

    Ramtron International Corporation

    Design of NV FRAM memories.

  • 7 months, Jul 2008 - Jan 2009

    Advisory Circuit Design Engineer

    IBM

    Technical Lead and individual contributor for the design of circuits and layouts on mixed-signal blocks.

  • 5 years and 6 months, Aug 2002 - Jan 2008

    Senior Memory Design Engineer

    ARM Inc.

    Design of SRAM/ROM memories. Supervision of layout resources.Mentoring of other engineers.Scheduling of design and verification tasks.

  • 4 years and 10 months, Jul 1997 - Apr 2002

    Component Design Engineer

    INTEL Corporation

    Design of Circuits and Layouts on microprocessors.Supervision of Layout resources.Silicon Debug

Ausbildung von Mansoor Mazhar

  • 1 year and 10 months, Aug 1995 - May 1997

    Electrical Engineering

    University of Southern California

    VLSI Design (Digital and Mixed-signal),Logic Design,Process fabrication,

Sprachen

  • English

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