Michael Kogan

Provide following services: - Layout (physical implementation) of digital IC: RTL to GDSII - Design for test solutions: setup of test concept, DFT insertion, test vector generation. - Ramp up of young engineer, start-up teams.

Onsite support of a customer from Automotive, Airspace and Defence market. Synthesis, DFT, Place&Route VHDL and FPGA Design

• Design and implementation of Hardware Programmable Components for Medical devices such as Computer tomography. • VHDL coding from spec • RTL verification and optimization for Xilinx FPGA and CPLD technologies. • Formal Verification and RTL quality check. • Adaptation of an old code to new spec and technology requirement • Validation of FPGA and CPLD implementation in lab. • EDA tools: ISE of Xilinx, HDL-Designer of Modelsim, Conformal LEC of Cadence

Provide following services: - Layout (physical implementation) of digital IC: RTL to GDSII - Design for test solutions: setup of test concept, DFT insertion, test vector generation. - Ramp up of young engineer, start-up teams. - FPGA design. - Sales representation.

• Project management: schedule and Statement of Work (SOW) definition and monitoring. • Technical lead of flat (one man), and hierarchical (multi engineers) designs. Work in international teams (3-6 engineers) with colleagues from Russia, Israel, China, India and Europe. • Physical implementation: RTL-synthesis trough Place and Route Layout implementation to Physical Verification and Tape-out to foundry of high-performance and ultra-low-power SOC devices at 180nm - 65nm technologies, for various customers

• Technical lead. • Layout of complex high speed (1 GHz) SOC designs with LVDS driver and receivers at LSI Logic 180nm technology, with Synopsys and LSI Logic tools, for a customer from Super Computer market in UK. • DFT service: scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation. • FPGA design with Xilinx SpartanII technology

• Technical lead. • Distributor of NEC and Chip Express ASIC vendors in Israel. • Front-end services: RTL validation and synthesis, scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation, preparation for layout. • VHDL coding from spec. for Telecommunication and Medicine clients. • ASIC to ASIC conversion from old to most recent ChipExpress technology • VHDL design for complex ASIC & FPGA designs. • Customer trainings, and flow setup.

• Distributor of Chip Express ASIC vendors in Israel • Front-end services: RTL validation and synthesis, scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation, preparation for layout. • FPGA to ASIC conversion from Xilinx and Altera to ChipExpress technology. • VHDL design for complex ASIC & FPGA designs.

Micro-Elektronik VHDL coding FPGA, CPLD design