Muralikrishna Sathyamurthy

Verilog RTL coding of digital blocks Sythesizing and performing simulations based on delays using Cadence irun Performing powerplanning, Place & Route (P&R) and CTS in Cadence Encounte

Digital block implementation of RF-ID smart sensor system, performing power profiling based on Cadence incisive and RTL compiler. Working closely with verification engineer in verifying the designed digital block. Performing P&R,CTS & STA of digital block.

Responsible for developing digital architecture for miniaturized low power RFID smart sensor system.

Hardware design of GPS receivers and Layout Design of Printed Circuit Boards primarily and was responsible for its validation and production.

Major in Basics of Microelectronics, Design and test of Microelectronic system, CMOS Analog, Optical Communication, Signal Processing and Advanced Programming techniques

Basic and Advanced topics in Electronics, Digital Communication, Satellite Communication ,Microwave Engineering and Measurements & Instrumentation