Padmaprasad Boopal

an individual contributor working on FPGA datapath designs for ATEs. Involved in design and implementation of functional blocks in Verilog/System Verilog, functional verifcation and hardware validation. Firmware development.

FPGA Development Module design and development in VHDL Design responsible Automated Test bench environment creation Functional verification STA and Timing Closure Hardware low level tests and on-board validation

ASIC RTL coding ASIC - FPGA porting and Validation SoC integration

Lattice FPGA based System on Chip development for Human Machine Interface Panels. ARM AMBA Bus Architecture - APB, AHB, AXI RTL design in VHDL and functional verification

Design of FPGA based Electronics Control Unit for Automotive. Matlab modelling for Hybrid Vehicles

Design and development of FPGA based hardware designs for Avionics.

System on Chip, Digital CMOS Design, FPGA Design, VHDL/Verilog, CAD, RF Electronics