
Naga Jayanth Avadhani Medicherla
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Naga Jayanth Avadhani Medicherla
- 11 Monate, Aug. 2024 - Juni 2025
Deputy Manger , plant Operations
Vikram Solar Ltd
• Implemented structured maintenance management and automated reporting across 2 production lines, reducing downtime by ~15% through better planning and spare-parts control. • Drove Lean and Kaizen projects on the module lines, cutting changeover time by ~30% via training plans, standard work, and skill development for operators. • Co-led the upgrade of the plant to a 1.5 MW TOPCon module line, coordinating with OEMs on installation, commissioning, and ramp-up to stable production.
- 1 Jahr und 1 Monat, Aug. 2023 - Aug. 2024
Graduate Engineer Trainee
Vikram Solar Ltd
• Supported maintenance and operations on solar module lines, building a strong understanding of end-to-end manufacturing and integration. • Analysed machine breakdowns and root causes and helped redesign the preventive maintenance schedule, increasing PM adherence from ~20% to ~80% in two months. • Contributed to downtime reduction of ~15% by improving failure analysis, documentation, and follow-up actions using Lean and Kaizen principles
Ausbildung von Naga Jayanth Avadhani Medicherla
- Bis heute 1 Jahr, seit Okt. 2025
Electromobility
Friedrich-Alexander-Universität Erlangen-Nürnberg
Related coursework: Vehicle Electrification, Power Electronic Systems and Control, Dynamics of Control Systems, Battery Systems, Wireless Communication, Decentralised Power Systems, Charging Infrastructure and Technologies.
- 4 Jahre, Juli 2019 - Juni 2023
Electrical Engineering
Indian Institute of Engineering Science and Technology, Kolkata
Related coursework: Power Systems and Protection, Electrical Machines and Power Electronic Drives, Digital & Analogue Electronics, Microprocessors and Microcontrollers, Embedded Systems, Signals and Systems, Control Systems. Project Thesis:- Implementing SVPWM on a Three-Phase VSI in an Embedded Platform Implemented SVPWM for a three-phase VSI in MATLAB/Simulink, analyzed responses under varying loads and LC filters, and developed block-level Verilog HDL models on Altera FPGA using Quartus.
Sprachen
Englisch
C1 (Fließend)
Hindi
C1 (Fließend)
Telugu
C2 (Verhandlungssicher / Muttersprachlich)
Deutsch
A1-A2 (Grundkenntnisse)
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