Nilay Ghumre

UNIPRO Verification  Verification of UNIPRO IP using System Verilog UVM.  RTL Debug.  Verification of L2 (Data Link Layer) Project MPHY Verification Description  Verification of MPHY IP using System Verilog UVM.  RTL Debug. Finding the RTL Bugs.  Writing Assertions for complete MPHY IP. Including Digital & Analog module interface assertion.  GLS Verification

Project UNIPRO Verification  Verification of UNIPRO IP using System Verilog UVM.  RTL Debug.  Verification of L2 (Data Link Layer) Project MPHY Verification  Verification of MPHY IP using System Verilog UVM.  RTL Debug. Finding the RTL Bugs.  Writing Assertions for complete MPHY IP. Including Digital & Analog module interface assertion.  GLS Verification

Working as Senior Design Verification Engineer:-  Verification of Graphics DDR PHY IP using System Verilog UVM.  Developing the Test Bench Environment for the various internal modules from scratch.  Writing X-Checker/Assertions for complete GDDR PHY Design  Data checkers for Internal Sub-Modules.  Power Aware Verification using NLP-UPF  Functional Coverage & Code Coverage from Scratch.

VLSI Design