Dr. Saikat Chatterjee

Design and verification of RTL using VHDL, Systemverilog and formal verification of OTN modules in an Industry project for 8 months

Research and development of a subthreshold operation compatible standard cell library and design of a system operating in subthreshold voltage synthesizable with the same standard cell library.

Leading a verification team with the responsibility of verification of ARM trustzone implementation in Wireless SoCs

Design and verification at module level and top level as well at the client location

Design and verification at module level

Standard Cell Library Design, RTL design in VHDL, Optimization of circuit performance(MATLAB)

Circuit Design, Layout Design, Digital VLSI