Stanislav Aziabin

Angestellt, Senior Hardware Engineer, (NDA)
Berlin, Deutschland

Fähigkeiten und Kenntnisse

Spacecraft Electronics
Schematic Capture
PCB design
Layout
Altium Designer
Hardware Engineering
Electronics Design
Mixed Signal Design
Electromagnetic compatibility (EMC)
Signal Integrity
Vector Network Analizer (VNA)
Time Domain Reflectometry
Eye Diagram Analysis
High-Speed Interfaces
CAN Bus
LVDS
Ethernet
SPI
I2C
RS-422
RS-485
STM32
Embedded Hardware
Optoelectronics
Laser Systems
ECSS Standarts
IPC
LTspice simulation
Polar Si9000
OrCAD Capture CIS
Siemens Teamcenter
Zuken E3 Series
Space technology

Werdegang

Berufserfahrung von Stanislav Aziabin

  • Bis heute 1 Jahr und 6 Monate, seit Apr. 2025

    Senior Hardware Engineer

    (NDA)

    • Reduced onboard interface error rate by developing an ECSS-compliant interface architecture. • Cut spacecraft parasitic EMI by introducing galvanic isolation and grounding requirements for subsystems derived from ECSS&experiments. • Defined the spacecraft-level electrical ICD. • Eliminated late-stage interface failures (on flight model) by codifying ECSS requirements for the onboard harness into an internal engineering standard. • Cut QA testing time by designing a test PCBs for the incoming QC station.

  • 6 Jahre und 8 Monate, Aug. 2018 - März 2025

    R&D Engineering Lead

    Ivel

    • Achieved ≤20 mm accuracy of the laser rangefinder by developing STM32F407 DSP brd, 1 ps res TDC, 10 ns GaN laser driver, APD, 300 MHz LNA, power supply. • Ensured a 3°/h FOG stability by developing power supply, TIA, 12/16-bit mixed-signal ADC boards, STM32F429 and Spartan DSP boards (SPI, RS-232, UBS2.0/Ethernet; led embedded software developing), laser driver. • Automated resonator characterisation (6-12× faster) by developing GaN laser driver, 14-bit DAC, LF driver, PIN-pd, LVDS/CML/SE converters.

  • 6 Jahre und 10 Monate, Okt. 2012 - Juli 2019

    Jr. Hardware Engineer → Lead Hardware Engineer

    Russian Space Systems

    • Delivered in-house radhard isolated DC/DC converters (33–50 W) into serial production: lead time 12–18 → 1–3 months, ~9× lower cost. • Halved mass & size of a stepper-motor drive by moving it from board level into a hermetical radhard multichip module. • Achieved ASIC SEU immunity via a triple-redundant control FSM with majority voting (Verilog), FPGA-verified. • Reduced testing time 12x by developing embedded software for an STM32F100 logger. • Full-custom layout of PLL and osc on CMOS gate array.

Ausbildung von Stanislav Aziabin

  • 5 Jahre und 10 Monate, Sep. 2010 - Juni 2016

    Design and Technology of Electronic Computing Devices

    Bauman Moscow State Technical University

Sprachen

  • Englisch

    B1-B2 (Gute Kenntnisse)

  • Deutsch

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