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Stuart Roberts

Angestellt, Senior Engineer, Digital IC Development, u-blox AG
Thalwil, Schweiz

Fähigkeiten und Kenntnisse

VHDL
Verilog
SystemC
FPGA
ASIC
Verification
Embedded Systems
Python
C
UVM
Digital IP
Team leadership
Technical Specification
Formal verification
System Design

Werdegang

Berufserfahrung von Stuart Roberts

  • Bis heute 10 Jahre und 11 Monate, seit Juli 2014

    Senior Engineer, Digital IC Development

    u-blox AG

  • 11 Jahre und 3 Monate, Apr. 2003 - Juni 2014

    Manager ASIC Design Group

    ACN SA

    Leading the development of large (multi-million gate), DSP-intensive ASICs and FPGAs (Xilinx Virtex-II, Virtex-4, Virtex-5 and Spartan-6) for powerline and Smart Grid communications products. Routinely created compact, high-performance RTL designs from highly abstracted MatLab code for complex functions such as Wavelet-OFDM signal transform, Viterbi decoder and digital resampler.

  • 1 Jahr und 8 Monate, Apr. 2001 - Nov. 2002

    Senior Systems Engineer

    Semtech International AG

    Responsible for the design and implementation of a complex (500,000 gate) SDH synchronisation status message handler and source prioritiser ASIC using 0.18 micron CMOS technology.

  • 1 Jahr und 9 Monate, Juli 1999 - März 2001

    Head of ASIC Development

    TransLumina AG

    Spearheaded the design, specification and development of high-performance (5 Gbit/s data throughput, 311 MHz clock frequency) ASICs and FPGAs for this telecommunications start-up specialising in optical high-speed transmission systems for next-generation access networks.

  • 9 Monate, Okt. 1998 - Juni 1999

    Consultant Engineer

    Martel GmbH

    Designed and implemented an ATM buffer manager and framer FPGA for a wireless broadband access system of a large telecommunications equipment manufacturer based in Sweden. Provided expert assistance in the development of customer’s system requirement specifications.

  • 2 Jahre und 9 Monate, Jan. 1996 - Sep. 1998

    Senior Engineer

    Ascom Tech AG

    Responsible for the specification and development of a high-performance, FPGA-based ATM buffer manager and framer of a hybrid fibre-coax transmission system for an external customer. Participated in a pan-European project to develop a broadband access system based on Very high-rate Digital Subscriber Loop (VDSL) technology. Responsible for the design and realisation of two large ASICs and a fast Medium Access Control (MAC) protocol for a 1.2 Gbit/s ATM Passive Optical Network (APON) prototype.

  • 1 Jahr und 7 Monate, Juni 1994 - Dez. 1995

    Consultant Engineer

    Fort Telecommunications

    Provided analogue and digital hardware expertise to the ATM switch development group of MET Commutation, including development of E1 and T1 PDH interface ports, an ATM F4 operations and maintenance (OAM) processor and a global synchronisation system for an ATM cross-connect.

  • 4 Jahre und 9 Monate, Sep. 1989 - Mai 1994

    Professional

    BT Laboratories

    Headed a team responsible for providing technical support to the specification, procurement and deployment of new digital transmission technology for BT's copper access network. Developed hardware and DSP software for some of the world’s first High-rate and Asymmetric Digital Subscriber Loop (HDSL and ADSL) transmission system prototypes.

Ausbildung von Stuart Roberts

  • 2 Jahre und 11 Monate, Sep. 1986 - Juli 1989

    University of Durham

Sprachen

  • Englisch

    Muttersprache

  • Französisch

    Gut

  • Deutsch

    Gut

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