Johannes Walter

Lead design and implementation of high-performance, resource-efficient GNSS signal processing IPs for the Xilinx Zynq platform. Verify functional correctness of mixed-language IPs using SystemVerilog and UVM. Manage release cycles and provide C firmware support to interface with hardware accelerators. Collaborate on GNSS receiver PCB design iterations.

Worked on an R&D team building the Universal Software Radio Peripheral (USRP), a market-leading Software-Defined Radio (SDR). Designed Verilog components to interface with high-speed RF transceivers and AXI4 IPs on Xilinx FPGAs. Built self-checking testbenches in SystemVerilog with constrained-random stimulus generation and performed coverage closure. Wrote Linux user-mode device drivers in C/C++ and C firmware for a USB 3.0 controller.

Improved radiation effect mitigation in the Large Hadron Collider (LHC) power converter control FPGAs. Designed radiation tolerant VHDL components and collaborated with the PCB design team. Performed functional verification with SystemVerilog/UVM/SVA and radiation tests to determine circuit reliability.

On an engineering team for the MedAustron cancer treatment project which operates an ion beam therapy center. Developed an FPGA-based interface PCB to ensure reliable communication over fiber optic links for the regulation loop. Wrote software in C/C++ for programming FPGAs remotely via Ethernet.

Worked for DICE, an R&D Center of Infineon Technologies. Created a SystemVerilog verification environment for register models within microprocessor cores using UVM. Assisted the component design team thoroughly verifying their implementations. Evaluated an OVM extension for SystemC to provide verification features during concept design.

Designed parameterizable FPGA prototyping environments for Near Field Communication (NFC) applications. Provided them as demonstrator and test setups to concept engineers to speed up design iterations.