
Syed Jawad Hassan
Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Syed Jawad Hassan
1) Designed 1.2V LDO using TSMC 65nm CMOS technology in Cadence Virtuoso, including error amplifier and voltage reference circuit, achieving precise line and load regulation. 2) Created layout and conducted DRC/LVS tests for LDO fabrication. 3) Performed post-layout tests to validate chip performance.
- 11 Monate, Juni 2017 - Apr. 2018
Associate Data Processing Engineer
GFK Etilize Pvt Ltd
1) Met daily data production targets with high quality. 2) Ensured error-free product data and obtained QC approval. 3) Demonstrated strong communication skills by responding to client queries through JIRA, facilitating effective collaboration and client support.
Ausbildung von Syed Jawad Hassan
- 7 Monate, Juni 2023 - Dez. 2023
Masters Thesis - Design & Comparative Analysis of Low Phase Noise Voltage Controlled Oscillator
Universität Paderborn
- Designed a 27 GHz low phase noise VCO in 130nm SiGe BiCMOS technology on cadence. - Explored and compared different oscillator architectures. - Iteratively optimized oscillator design and implemented noise filter in current mirror. - Achieved superior phase noise of -111.48 dBc/Hz at 1 MHz offset and a tuning range of 1.0 GHz. - Utilized an emitter follower as a buffer. - Conducted pre and post-layout simulations, followed by electromagnetic (EM) simulations to ensure robustness.
- 6 Monate, Mai 2020 - Okt. 2020
Low Dropout Voltage Regulator (LDO) - Project
Universität Paderborn
- Designed a 1.2V LDO using TSMC 65nm technology on cadence with an active area of 0.018μm2. - For LDO, error amplifier and voltage reference circuit was fabricated. - Observed line regulation ranging from 1.25V - 2.3V with 100μA load. Obtained load regulation in the range of 50μA - 1mA with 1.2V supply voltage. - Dropout voltage was determined to be 500mV. - Layouted the complete chip and have them tested using layout verification tools like DRC and LVS.
- 6 Monate, Nov. 2019 - Apr. 2020
Data Correction Methods - Project
Universität Paderborn
- A stream of temperature data with missing values were provided, with an objective to predict data gaps. - Several data analytics techniques like mean substitution, moving average, machine learning were studied and implemented. - Results extracted from these techniques were effectively generated and compared.
- 5 Jahre und 3 Monate, Okt. 2018 - Dez. 2023
Electrical Systems Enginnering
Universität Paderborn
Major courses: 1) Circuit and system design 2) Modelling and simulation 3) Mechatronics 4) Integrated circuits for wireless communication 5) Fast integrated circuits for wireline communication
- 1 Jahr, Nov. 2015 - Okt. 2016
Hovercraft - Final Year Project
Sir Syed University of Engineering and Technology
- Designed a prototype hovercraft as a final project in bachelor's. - Modeled its mechanical architecture from scratch. - BLDCs motors, ESCs, servo motor, propellers & lipo batteries were deployed. - Automated it via GPS. - Arduino mega, AVR studio, Bluetooth module, Proteus & Android app were utilized.
- 2013 - 2016
Electronics Engineering
Sir Syed University of Engineering and Technology
Major courses: 1) Basic electronics 2) Electronic devices and circuits 3) Power electronics 4) Embedded system design and applications 5) Industrial electronics
- 2010 - 2012
Pre-Engineering
D.J. Sindh Government Science College
Sprachen
Englisch
Fließend
Deutsch
Gut
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