Thomas Klein

Verification team lead. Mentoring, verification automation, flow development, test plan creation, implementation and debug. Working on ESA aerospace projects for environment monitoring.

FPGA Design with Xilinx chips Training and Support for Xilinx Customers

Build and bring-up of emulation models for SoC designs on Mentor Veloce D1/D2 platform. Development and integration of emulation collateral (trackers, xactors). Customer support and training on emulation tool usage. Emulation model build flow enhancements. Platform specific design optimization for improved emulation resource usage.

RTL design for a new IA processor: Behavioral and structural RTL coding of Integer Unit components; Low-level test code. Pre-Silicon validation of Intel architecture features (VT) and debug interfaces (PDM) on modern x86 processors (Core i3/5/7): Test plan writing, test implementation, cluster and full-chip simulations, bucketing, failure analysis (RTL, Microcode, tools, environment), bug fix proposals. Post-Silicon validation of 10G interface of optical networking chip. Thermal chip testing.

Jun 2004 - Nov 2004: Working for Intel GmbH, Braunschweig - Extension of an FPGA design for testing of a telecommunication ASIC: 10 GBit/s PRBS generator and checker. Dec 2004 - Jan 2006: Working for MTU Aero Engines AG, Munich - Development and test of an electronic avionic device (EPMU): Prototype assembly; HW and SW interface component tests. Feb 2006 - Mar 2006: Working for BHTC, Lipstadt - Test automation for automobile thermal and ventilation air control devices.

Implementation of digital FIR filters for Altera FPGAs

Migration of parts of an ASIC design (DCDA controller) into a Xilinx FPGA for prototyping.