venkat ramana reddy yellela

Bis 2024, Working Student, Fraunhofer IEE

Skills

PowerFactory
Elektrotechnik
Energietechnik
Energy management
Smart Grid
Electrical Engineering
power factory
Load Flow Analysis
Real-Time Systems
BESS
Renewable Energy
Energy demand management
Optimization
Power Factory
MatLab
Simulink
Energy
German
Python
Energy storage
English Language
Electrical Powering Systems
Energy supply
Engineering

Timeline

Professional experience for venkat ramana reddy yellela

  • 7 months, Mar 2025 - Sep 2025

    Master Thesis

    KIT - Karlsruher Institut für Technologie

    Projekt Name: BI-FLOW TOPIC: Operational optimization of a Hybrid Energy Storage System with Power- Heat using Heuristic Algorithms. Core Skills: Python, Scipy, Pyomo, Gurobi, ipopt

  • 3 months, Dec 2024 - Feb 2025

    Working Student

    KIT - Karlsruher Institut für Technologie

    Project Name: ESiP (Energy Storage in Production) -implemented a Mixed Integer Linear Programming (MILP) algorithm, focusing on economic and technical aspects for the ESIP project, and documented the results. -Developed a model based design of a bidirectional converter for active power transfer between battery and grid with a dq-based control strategy in MATLAB/Simulink

  • 6 months, May 2024 - Oct 2024

    Working Student

    Fraunhofer IEE

    Project Name: COMBI Power -Developed average model(buck-boost), switching model and DQ-model of three-phase converters and simulated using PLECS. -Developed DQ control algorithms and simulated in MATLAB/Simulink. -Designed and implemented PWM switching circuits. -Performed Stability Analysis

  • 3 months, Feb 2024 - Apr 2024

    Working Student

    KIT - Karlsruher Institut für Technologie

    Project Name: RESUR - Modeled 84 substations in the Hamburg area. - Annotated the substations with Label Studio software. - Performed load flow analysis

  • 6 months, Apr 2023 - Sep 2023

    Intern

    KIT - Karlsruher Institut für Technologie

    • Developed a three-phase inverter model in MATLAB/Simulink and deployed it on FPGA. • Upgraded the whole system for controller-in-loop applications. • Defined analog and PWM digital interfaces in the workflow to have a communication between simulink model, opal-rt module and imperix B-box controller. • Simulated the system using RT Lab on OP4510, interfacing with Imperix B-Box controller. • Integrated and commissioned Imperix hardware in hardware-in-the-loop (HiL-Testing) simulation.

  • 6 months, Apr 2022 - Sep 2022

    Intern

    KIT - Karlsruher Institut für Technologie

    • Performed load flow analysis and short circuit calculations using DIgSILENT Power Factory. • Modeled AC and DC faults in HVDC transmission lines using PSCAD/EMTDC. • Calculated the numerical field of bushing with and without capacitive layers using COMSOL.

  • 2 years, Aug 2016 - Jul 2018

    Electrical Engineer

    MNR Electricals

Educational background for venkat ramana reddy yellela

  • 4 years and 11 months, Nov 2020 - Sep 2025

    Electrical Power Systems

    Karlsruher Institut für Technologie

Languages

  • English

    C1 (Fluent)

  • German

    B1-B2 (Good)

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