Alberto Celin

Firmware development for cameras and embedded systems integrated in scanners for wood and food.

Digital design and verification of chips used for audio and haptics applications in portable devices and wearables.

Digital design and verification of chips used for audio and haptics applications in portable devices and wearables.

R&D on embedded systems for off-highway vehicles. Design, configuration and integration of vehicular prototype systems. Firmware development. Rig and start-up of test benches for control units and drivelines.

The internship consisted in designing, synthetizing and simulating a testing framework for an asynchronous Network-on-Chip switch. It implied the creation of RTL models in Verilog and the development of an asynchronous design flow using Synopsys Design Compiler. The obtained post-synthesis model was simulated using ModelSim and the simulation was managed by an automated system, developed in Perl language, for the injection of stuck-at faults in the netlist under simulation.

The internship tasks included the modification of a design flow using Synopsys Design Compiler in order to add a scan-chain based testing framework to a switch for Network-on-Chip. TetraMAX ATPG was used to generate deterministic test patterns for the post-synthesis switch, RTL models were developed in Verilog and ModelSim was employed to simulate the system.

Thesis: "Design and Implementation of a Testing Strategy for Asynchronous Networks-on-Chip Immune to Delays Variability". Advisor: Prof. Davide Bertozzi. Final Mark: 103/110

Tesi: “Comparative Analysis of Built-In Self-Testing Techniques for Networks-on-Chip with and without Scan-Chain”. Advisor: Prof. Davide Bertozzi. Final mark: 97/110