Aleena Varghese

Physical Design Engineer with expertise in STA & Physical Verification With over 4.5 years of professional experience in the VLSI industry, I specialize in Physical Design, STA and Physical Verification. I have in-depth knowledge and experience in the end-to-end flow from RTL/netlist to GDSII, including design floorplanning, timing budgeting, and convergence to sign-off quality. My expertise also extends to IO-Planning, Signal Integrity, DFM, IR-Drop, EM, DRC, LVS, and Bump planning and RDL implementation.