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Anudeep Teegala

Angestellt, Design Verification engineer, SiFive
Hyderabad, India

Skills

Verilog
system verilog
uvm
python
c
arduino
Computer Architecture
Digital electronics
Communication skills
Team work

Timeline

Professional experience for Anudeep Teegala

  • Current 4 years and 8 months, since Apr 2021

    Design Verification engineer

    SiFive

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