Dirk Baumann

- Entwicklung, Implementierung und Verifikation von Analogem Fullcustom physical Design - Entwicklung/ Implementierung von physical Design Architekturen unter Berücksichtigung von elektrischen und anderen Spec Anforderungen wie z.B ESD, Temperature, Lifetime - Verifikation des physical Design nach definierten Sign Off Kriterien - Abschätzung und Planung von Arbeitspaketen (für Projekt Planung und SoW Erstellung) - I/O fullcustom physical design, fully verified and documented according to Specification

For IPD SPOC LG Layout service for block level (main task): · Charge Pump · High side switch gate driver · PMU power management unit · AMS layout activities for several Projects · Layout verification according to sign off guidelines (DRC LVS ANT ERC) · Interaction with circuit designer for best area and performance · Layout reviews · Regular reports of assigned tasks on progress and effort estimations

28 nm Radar 77GHz Chip process: TSMC 28 nm layout environment: cadence 6.1.7 virtuoso XL verification: calibre

1. project support layout for tapeout preperations process: tsmc 40nm layout environment: cadence 6.1.8 virtuoso XL verification: calibre 2. project Top level layout, Laiser Diode Driver Layout, Bias, Voltage Monitor, ADC & outhers , Tapeout resonsible process: elmos 350nm layout environment: synopsis cdedigner verification: icv 3. project high speed mux up to 8 GHz layout process: tsmc 40nm layout environment: cadence 6.1.8 virtuoso XL verification: calibre

high voltage switch capacitor layout process: TSMC 22nm layout environment: cadence 6.1.8 virtuoso XL verification: IC Validator

26GHz Mux layout process: globalfoundries 22nm - FD-SOI layout environment: cadence 12.3 virtuoso XL verification: calibre

77GHz Radar Sensor process: 28 nm layout environment: cadence 6.1.1 virtuoso XL verification: calibre Testchip process: tsmc 16mm FinFET layout environment: cadence 6.1.1 virtuoso XL verification: calibre

process: TI 130nm layout environment: cadence 6.1 virtuoso GXL verification: assura layout & verification of ASM blocks

hearing aid ic process: tsmc 65nm layout environment: synopsys custom-compiler, maxwell verification: synopsys icvalidator layout & verification of IO cells for an digital dsp

process: TI 130nm layout environment: cadence 6.1 virtuoso GXL verification: calibre, assura layout & verification of ASM blocks

create testcases for package drc evaluation convertig data for different packages( KA, dxf, xas, gds) update packages with new chips layout of bonddiagram

ams 350nm process, layout for RF-ID chip, RX, wakeup, bandgap, oo-amps .... RFID layout Layout Environment: Cadence 6.1 Verification: Calibre

ST BCD9S prozess high voltage ( - 50V) analog layout Layout Environment: Cadence 6.1.6 Verification: Calibre

CMOS14 SOI prozess high voltage ( 50V) analog layout Layout Environment: Cadence 6.1.x Verifikation: Cadence PVS 12.x

layout of an DPLL in 2 project 65nm, 28nm Layout Environment: Cadence 6.1.x Verifikation: Calibre

toplevel, module & blocklevel analoge mixed signal layout & verification

Flip Chip Cadence Encounter Layout ( Placement, Routing, Power Grid etc.) TCL Progammierung Verifikation mit DRC/ LVS/ ERC analog layout von IP

mixed signal ADC ASIC in BiCMOS Technologie - Floorplanning - Power & Powerrouting - man. Device Placement nach analogen Constrains( matching, Symmetrie, Hf, etc.) - man. Routing von impedanzkontrollierten HF-Pfaden( diff. Pair, Stripline) - Verifikation von Layout-Zellen, Blöcken und Top-Level mit Cadence Diva, Assura( DRC, LVS, Antennacheck, Density Check. etc. ) - Postprocessing( Metal-Fill, Active-Fill, Slit-Generation, etc. ) - Tapeout Prozedur