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Dr. Farhan Rasheed

Angestellt, Principal Product Engineer, Cadence Design Systems
Dortmund, Deutschland

Fähigkeiten und Kenntnisse

Python
Modelling
Physical Design
EDA/CAD
Optimization
Simulation
Analog Circuits
Cadence SKILL
Cadence
DRC
Machine learning
LVS
Parasitic Extraction (PEX)
Electronic Design Automation
perl
C/C++
Technology development
Device development
Modeling
Circuit design
SPICE
process design kit (PDK)
Electronic Design Automation (EDA)

Werdegang

Berufserfahrung von Farhan Rasheed

  • Bis heute 1 Jahr und 11 Monate, seit Aug. 2023

    Principal Product Engineer

    Cadence Design Systems

  • 3 Jahre und 1 Monat, Juli 2020 - Juli 2023

    Entwicklungsingenieur - Hardware Design and Support

    Elmos Semiconductor SE

    - Technology evaluation through demonstrator development, qualification, and documentation. - Assisting in the integration of NVM IPs in different ASIC projects. - Measurement data analysis for NVM memory cells for the automotive product qualification (AEC-Q100). - ROM code development for functional verification of modules (SPI, Watchdog, SWD) in a System Design (product) and functional verification via mixed-model simulation. - Development of behavioral models (Verilog, Verilog-A) for analog circuits

  • 3 Jahre und 6 Monate, Jan. 2017 - Juni 2020

    Modeling, Technology Development and Physical Design Automation

    Karlsruher Institut für Technologie (KIT)

    - Circuit design and simulation of test circuits using Cadence tools (Virtuoso and Spectre). - Process Design Kit (PDK) development for an emerging technology including standard cells and parametrized cells (pcell) library. - Compact modeling (SPICE/Verilog-A) and simulation of active devices and circuits. - Automation of Synopsys design compiler and Cadence Virtuoso (routing) using Python, Tcl and SKILL scripting. - RTL Synthesis, timing analysis, placement and routing optimization.

  • 6 Monate, Apr. 2016 - Sep. 2016

    Internship and Master Thesis: Design of a Non-Volatile Memory Cell

    X-FAB Dresden GmbH & Co. KG

    :: Master Thesis (Apr 2016 - September 2016): - Analysis and modification of the cell for better process robustness including schematic, layout, layout simulation, LVS and DRC check. - A comprehensive report in a form of thesis. :: Working Student: Analysis and Simulation of Analog Blocks (November 2015 - March 2016) - Development of scripts (perl and SKILL) for automation of ADE-XL simulation, data extraction from simulation results and summary on HTML webpage.

  • 1 Jahr und 10 Monate, Dez. 2013 - Sep. 2015

    Intern Student: Physical Design Methodology (EDA/CAD)

    GLOBALFOUNDRIES

    - Development of scripts (SKILL and perl) for regression of Cadence tools based Electronic Design Automation (EDA) component flows. - Basic knowledge of Analog/Mixed Signal (AMS) reference flow silicon validation and 3 sigma corner verification.

Ausbildung von Farhan Rasheed

  • 3 Jahre und 7 Monate, Jan. 2017 - Juli 2020

    Computer Engineering

    Karlsruher Institut für Technologie

    Physical Design Automation Technology Development Compact Modeling Circuit Design and Optimizations

  • 3 Jahre, Okt. 2013 - Sep. 2016

    Nanoelectronics Systems

    Dresden University of Technology

    Master Thesis: Analysis and modification of a single cell non volatile memory structure for analog trimming purposes based on a floating gate topology realized using a standard mixed signal 0.35µm CMOS technology.

  • 4 Jahre, Okt. 2008 - Sep. 2012

    Electrical Engineering

    Hamdard university

    Electronics

Sprachen

  • Englisch

    Fließend

  • Deutsch

    Grundlagen

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