
Dr. Farhan Rasheed
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Fähigkeiten und Kenntnisse
Werdegang
Berufserfahrung von Farhan Rasheed
- Current 2 years and 10 months, since Aug 2023
Principal Product Engineer
Cadence Design Systems
- 3 years and 1 month, Jul 2020 - Jul 2023
Entwicklungsingenieur - Hardware Design and Support
Elmos Semiconductor SE
- Technology evaluation through demonstrator development, qualification, and documentation. - Assisting in the integration of NVM IPs in different ASIC projects. - Measurement data analysis for NVM memory cells for the automotive product qualification (AEC-Q100). - ROM code development for functional verification of modules (SPI, Watchdog, SWD) in a System Design (product) and functional verification via mixed-model simulation. - Development of behavioral models (Verilog, Verilog-A) for analog circuits
- 3 years and 6 months, Jan 2017 - Jun 2020
Modeling, Technology Development and Physical Design Automation
Karlsruher Institut für Technologie (KIT)
- Circuit design and simulation of test circuits using Cadence tools (Virtuoso and Spectre). - Process Design Kit (PDK) development for an emerging technology including standard cells and parametrized cells (pcell) library. - Compact modeling (SPICE/Verilog-A) and simulation of active devices and circuits. - Automation of Synopsys design compiler and Cadence Virtuoso (routing) using Python, Tcl and SKILL scripting. - RTL Synthesis, timing analysis, placement and routing optimization.
- 6 months, Apr 2016 - Sep 2016
Internship and Master Thesis: Design of a Non-Volatile Memory Cell
X-FAB Dresden GmbH & Co. KG
:: Master Thesis (Apr 2016 - September 2016): - Analysis and modification of the cell for better process robustness including schematic, layout, layout simulation, LVS and DRC check. - A comprehensive report in a form of thesis. :: Working Student: Analysis and Simulation of Analog Blocks (November 2015 - March 2016) - Development of scripts (perl and SKILL) for automation of ADE-XL simulation, data extraction from simulation results and summary on HTML webpage.
- 1 year and 10 months, Dec 2013 - Sep 2015GLOBALFOUNDRIES
Intern Student: Physical Design Methodology (EDA/CAD)
- Development of scripts (SKILL and perl) for regression of Cadence tools based Electronic Design Automation (EDA) component flows. - Basic knowledge of Analog/Mixed Signal (AMS) reference flow silicon validation and 3 sigma corner verification.
Ausbildung von Farhan Rasheed
- 3 years and 7 months, Jan 2017 - Jul 2020
Computer Engineering
Karlsruher Institut für Technologie
Physical Design Automation Technology Development Compact Modeling Circuit Design and Optimizations
- 3 years, Oct 2013 - Sep 2016
Nanoelectronics Systems
Dresden University of Technology
Master Thesis: Analysis and modification of a single cell non volatile memory structure for analog trimming purposes based on a floating gate topology realized using a standard mixed signal 0.35µm CMOS technology.
- 4 years, Oct 2008 - Sep 2012
Electrical Engineering
Hamdard university
Electronics
Sprachen
English
C1 (Fließend)
German
A1-A2 (Grundkenntnisse)
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