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Gian-Luca Brazerol

Angestellt, Wissenschaftlicher Assistent, IMES OST
Rapperswil SG, Switzerland

Skills

FPGA Design
Vivado
VHDL
PCB Design
Sigasi
Time-To-Digital Converters
Efinix
Xilinx
Efinity
Vitis
Python
Data Science
Deep Learning
ASIC Design
Cadence
Digital Signal Processing
Microelectronics
Quartus
Elektrotechnik
Hardware

Timeline

Professional experience for Gian-Luca Brazerol

  • Current 1 year and 11 months, since Sep 2023

    Wissenschaftlicher Assistent

    IMES OST

Languages

  • German

    First language

  • Dutch

    Fluent

  • English

    Fluent

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