Ali Shan

Working on RTL design (IP catalog) and verification using Verilog and System Verilog Working on the IP Catalog of Open Source EDA Tool Working on open Source SystemRDL for CXL3.0 and PCIe 6.0 Experience with scripting languages such as TCL/Python and Bash , Makefile etc. Hands on RTL simulation tools including VCS, Verdi, Verilator, and Icarus

Experience with FPGA and CPLD development tools from Xilinx Vivado, Vitis HLS, Altera, and Simulink /HDL coder. DSP and Communication algorithm implementation in Verilog and VHDL like DDS, FIR filter, FFT and IFFT, Analog and digital Modulation schemes, Convolutional encoder, Viterbi decoder, Interleaver and de-Interleaver, AXI4 and FIFO, etc. Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog) and debug the design via simulation tools

Strong logic design background with an ability to do RTL design and verification using Verilog and System Verilog Experience with system on Chip (SOC) Architecture, Memory & processor subsystems, and Peripheral interconnects. Experience with bring-up and debugging of FPGA based designs Designed and implementation of SOC protocols UART, I2C, SPI, I2S, etc. Programming (C/C++) and scripting (Perl/Python) knowledge is a plus Directing activities belong to projects in the field of Embedded syste

Programmed 8 bit AVR, ARM4 Cortex 32 bit (STM-32), Raspberry pi 3, and PYNQ (FPGA) Experience with AD converters and microprocessor interface to FPGA’s Experience with microcontrollers and standard bus protocols, including UART, RS232,I2C, SPI, USB etc Designed professional PCB, PCB reverse Engineering, and troubleshooting Altium,Proteus, and Eagle Put hands-on several different Simulation Software as MATLAB, Simulink, and PSpice