Heenakousar Nadaf
Bis 2020, SOC Design Engineer, Intel Technology India Pvt Ltd
Bremen, Deutschland
Werdegang
Berufserfahrung von Heenakousar Nadaf
3 Jahre und 6 Monate, Aug. 2016 - Jan. 2020
SOC Design Engineer
Intel Technology India Pvt Ltd
Job role includes pre-silicon functional validation of tests to verify that the system meets design requirements. Creating test plans for RTL validation, writing of sequences/code using system verilog, OVM/UVM in Gvim editor, defining and running simulation models in VNC viewer, debugging using Verdi Simulator and to find corrective measures for failing RTL tests. Analyzing of results obtained and modify the test accordingly.
7 Monate, Feb. 2016 - Aug. 2016
Internship
Intel Technology India
1.Investigating new methods to fill in gaps in SOC Architecture Power/Performance modelling 2.Post Silicon Architecture and validation Tool
10 Monate, Dez. 2013 - Sep. 2014
Associate Engineer Trainee
Tata Consultancy Services, India
Manuel Testing of Vehicle Body Control features for Jaguar and Land Rover(JLR) project.
Ausbildung von Heenakousar Nadaf
2 Jahre und 2 Monate, Apr. 2014 - Mai 2016
VLSI Design and Embedded Systems
PES University, Bangalore
Digital VLSI Design Advanced Embedded Systems VLSI Process TEchnology Digital system design using Verilog Design of analog and mixed mode VLSI Circuits Low power VLSI Design VLSI Testing and Verification
3 Jahre und 10 Monate, Aug. 2009 - Mai 2013
Electronics and Communication Engineering
Vishveshwarya Institute of Technology
Embedded systems Digital circuits CMOS and VLSI Verilog Signals and System
Sprachen
Englisch
Fließend
Deutsch
Gut