Jaimini Nagar
Bis 2019, Project Trainee, Space Application Center, Indian Space Research Organization
Rotterdam, Niederlande
Über mich
VLSI Design and Verification Trainee at Maven Silicon 🎓 M.tech in Microelectronics and VLSI Design 📝 Believe in continuous learning and enhance the skill 🏆 Having an opportunity, I prefer to pursue PhD.
Werdegang
Berufserfahrung von Jaimini Nagar
5 Monate, Jan. 2019 - Mai 2019
Project Trainee
Space Application Center, Indian Space Research Organization
5 Monate, Jan. 2019 - Mai 2019
Project Trainee
Space Application Center, Indian Space Research Organization
Ausbildung von Jaimini Nagar
2 Jahre, Aug. 2017 - Juli 2019
Electronics and Communication Engineering
MIT-ADT University
Specialization in Microelectronics and VLSI Design with subjects area of Analog CMOS Design, Digital VLSI Circuit, Low Power VLSI Design, ASIC Design, Digital Design Techniques, Mixed Signal VLSI Design, Low power VLSI design
7 Jahre und 5 Monate, Aug. 2008 - Dez. 2015
Electronics and Communication Engineering
The Institution of Engineers (India)
Digital hardware design, Electronics circuit, Communication engineering, Solid state physic and devices, Electronics devices and circuits
2 Jahre und 11 Monate, Dez. 1998 - Okt. 2001
Electrical engineering
R. C. Technical Institute
Electrical circuits, Electronics circuits, Basic electronics, Electrical machines
Sprachen
Englisch
Fließend
Deutsch
Grundlagen
Hindi
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