Jerry Yang

Basic

Angestellt, Senior R&D Engineer, Nordic Semiconductor

Trondheim, Norway

Skills

DFT
Scan
MBIST
STA
ATPG
RTL
ATE
Perl
C/C++
Linux

Timeline

Professional experience for Jerry Yang

  • Current 4 years and 10 months, since Apr 2017

    Senior R&D Engineer

    Nordic Semiconductor

  • 7 years and 8 months, Sep 2010 - Apr 2018

    Senior DFT Engineer

    NVIDIA

    DFT implementation, verification and ATE bring-up for graphic and SoC chips. Mainly focus on scan and mbist.

  • 10 months, Nov 2009 - Aug 2010

    Senior DFT Engineer

    Global UniChip

    DFT project implementation and ATE bring-up. GUC is a design service company including front-end to back-end process. DFT specs are from the negotiation between GUC and customers. I once experienced storage chip of ADATA, Soc chip and network communication chip of CSR. Focus on scan and mbist.

  • 4 years and 1 month, Oct 2005 - Oct 2009

    DFT Engineer

    VIA Technologies

    My first job. VIA products are north/south bridge chipsets for Intel and AMD. Established ATPG of stuck-at fault and transition fault to ATE to reduce test pattern volume and raise yield and defect coverage. Also established scan compression flow with Synopsys solution and IEEE1500 insertion flow with in-house tool. Work closely with back-end teams for physical data. Design Compiler, TetraMAX, STA with PrimeTime/TimeCraft, and RTL/gate-level verilog implementation are fundamental.

  • Senior DFT Engineer

    NVIDIA

Educational background for Jerry Yang

  • 2 years, Jul 2003 - Jun 2005

    Electrical Engineering

    National Tsing-Hua University

    Thesis: Scan chain hold time diagnosis with statistical analysis. Project: VCD waveform dumper with C++ (SpringSoft)

  • 4 years, Jul 1999 - Jun 2003

    Electrical Engineering

    National Tsing-Hua University

    Project: JTAG2000 decoder with verilog.

Languages

  • English

    Fluent

  • Chinese

    First language

Interests

Tennis
Football
Guitar
Cooking
Baking
Coffee blewing

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