Jerry Yang

DFT implementation, verification and ATE bring-up for graphic and SoC chips. Mainly focus on scan and mbist.

DFT project implementation and ATE bring-up. GUC is a design service company including front-end to back-end process. DFT specs are from the negotiation between GUC and customers. I once experienced storage chip of ADATA, Soc chip and network communication chip of CSR. Focus on scan and mbist.

My first job. VIA products are north/south bridge chipsets for Intel and AMD. Established ATPG of stuck-at fault and transition fault to ATE to reduce test pattern volume and raise yield and defect coverage. Also established scan compression flow with Synopsys solution and IEEE1500 insertion flow with in-house tool. Work closely with back-end teams for physical data. Design Compiler, TetraMAX, STA with PrimeTime/TimeCraft, and RTL/gate-level verilog implementation are fundamental.

Thesis: Scan chain hold time diagnosis with statistical analysis. Project: VCD waveform dumper with C++ (SpringSoft)

Project: JTAG2000 decoder with verilog.