Julien HARRAULT

As a Wafer Test Process Engineer, I'm playing a key role between local business lines and BE Test concerning wafer test process & technology development, improvement and standardization. On top of that, I'm providing consultancy support to Business Lines to match Die Design and Wafer Test Process flow for New Product Introduction with BE Test process capability. I'm the key entry point in determining the impact of process changes in FE and BE Assembly on BE Wafer Test processes.

Director's deputy of the Business Unit ‘Test & Packaging’: • Project Manager including: - Mgt of a Test developers team and Hardware design team. - Mgt of the qualification phase in common with the Quality department. - Release for production. • Packaging specialist (BGA, PGA, QFN,...) • Main Test Customer Interface • I.c.o developing the Operational Plan and Strategic Plan. • Operational support to finance for tracking incomes and ‘Cost of Test’. • ISO 9001 and ISO TS 16949 internal auditor.

Responsible of more than 600 probe cards used to test all manufactured chips : (Budget: $2.5M) • Coordinator of 3 engineers and 5 technicians. • Responsible of new Electrical Boards Design. • Qualification, debug and repair on different types of probe cards (Membranes, µ-spring, Vi-Probe, Cobra and Cantilever) • In charge of ‘Probing Cost reduction’ and Department budget. • ‘WaferWorx’ expertise (RUDOLPH’s tool). • ISO 9001 and IS0 TS 16949 internal auditor.

Main courses are: System Automation, Material Engineering, Automated production, Electronics, Design of Industrial Products and Systems, Design (CAD CAM)…