Praveen Roy

Member of physical design team to design a processor. Synthesis, Scan Insertion, Floorplanning for multi-voltage design, Placement, clock tree synthesis, Routing and sign-off timing analysis for a design running on 1.2GHz frequency, 14nm FinFet technology for three blocks, the complex block being an instance count 1 Million

I worked on eight projects for the multiple clients in this period to design a quad core and an octa core mobile processor running on a clock frequency >1.2GHz. My responsibilities include to work and lead a team of 2-5 engineers on RTL Design, Synthesis, Scan Insertion, Floorplanning, Placement, clock tree synthesis, Routing and sign-off timing analysis implemented technologies from 130nm to 28 nm TSMC technology with a block instance count ranging from 30K to > 1Million instance count.

My responsibilities are Synthesis, Floorplanning, powerplanning, placement, optimization, clock building and routing with clock running at 250 MHz and 10 macros on 180nm technology

RTL Design of various IPs in Verilog and VHDL, Fixing timing issues, Synthesizing the design, Assigning pins and generating bit files, On board debugging bug fixing.

Low Power VLSI Design, Digital System Design, High Speed VLSI Design