Dipl.-Ing. Ralf Gaisbauer

Digitial architecture design between protocol and analogue layers for High Speed Mixed Signal PHY RTL design and front-end implementation, verification, sign-off into sub-micron ASIC techologies Testchip design and FPGA prototyping Verification planning and testbench design Mixed signal verification Project tracking/management and design documentation Participation and contributions to MIPI standardization consortium, PHY Workgroup

3G, LTE Platform design Development of virtual—prototyping simulation models for 3G mobile baseband platform (C++)

Digital design architect and design lead for digital PHY IPs, top-level verification and integration, sign-off and testchip design - MIPI D-PHY and M-PHY - V-By-One Tx PHY - DisplayPort 1.2 Development of the digital front-end flow in an automated, IP based SoC design environment - Digital front-end design part pilot projects (65nm/45nm technology demonstrator SoC) - Logic synthesis and STA sign-off for a pilot project with focus on Advanced Low Power (ALP)

Verifcation lead for 3G-UMTS modem SoC design. Technical project management and customer interface Reprensatative project lead.

RTL design, implementation and verification of digital SoC designs in ASIC or FGPA technologies for wireless applications: GSM, UMTS-FDD, DVB and proprietary modems - Technical project lead - Methodology development and transfer to customers - Pre-sales support for Synopsys EDA tools - Post-sales customer support for selected Synopsys DesignWare Cores

Design Engineer, RTL design and ASIC backend

ASIC Design Engineer RTL Design and ASIC backend for automotive and multimedia applications. Partially project responsibility, last position as representing group leader

Timely limeted employment. Implementation of digital signal processing algorithms in VHDL.

Digital design, computer arithmetic