Saravanan KV
Skills
Timeline
Professional experience for Saravanan KV
- Current 4 years and 8 months, since Nov 2020
Post Silicon Validation Engineer
Tessolve Semiconductor GmbH
Test Plan and Test Program development from scratch and debug for Automobile devices (LDO Block,Static Parameters of ADC and DAC using RDI (SMT-7) in Verigy-93K Tester. Test Program Integration and Test time reduction of all the blocks. Good Knowledge in debugging in SMT-7 (V-93K Tester) - RDI Programming Having good Knowledge on High Power Instruments (PVI-8,AVI-64,FVI-16) ,digital instrument(PS1600) and PMUX instrument. Developed Scripts using OpenPyXl and Pandas in Python for handling CSV,Excel files.
- 2 years and 6 months, May 2018 - Oct 2020
Post Silicon Validation Engineer
Tessolve Semiconductor Private Limited
Test Program development from scratch for PMIC devices(LDO Block,Buck Block ) using RDI (SMT-7) and Java (SMT-8) in Verigy-93K Tester. Good knowledge in Java and RDI Programming in SMT-7. Having good Knowledge on Digital instrument(PS1600). Trained Engineers in Java Programming Language.
- 4 months, Jan 2018 - Apr 2018
Post Silicon Validation Engineering Intern
Tessolve Semiconductor Private Limited
Post Silicon Validation Engineer Intern. Worked on Mixed Signal device (DAC) in ATE platform (Tester : Credence Sapphire). Gained Knowledge on Test Program development,debugging and analyzing test Parameters.
Educational background for Saravanan KV
- 4 years and 1 month, Jul 2014 - Jul 2018
Electronics and Communication Engineering
Mepco Schlenk Engineering College
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