Stephen Mueller

Founded berlin semiconductor, a chip design consulting company providing services worldwide.

Managed a team of 80 engineers designing complex mobile application processor SoC's in process nodes down to 20nm. Over the years, I managed or led a variety of chips in the applications processor (cellular), networking, touch screen controller, mobile digital TV, and IP phone markets. My team was responsible for the design, verification, implementation, tape out, and production release of our chips.

Managed a team of engineers developing an ASIC to power Coactive's home gateway product. The chip consisted of an ARM9 CPU with standard AHB/APB buses, an SDRAM controller, various peripherals, and another ARM9 dedicated to a DSP subsystem responsible for powerline communication in the home.

Worked with customers to integrate the RTL for our IP product into their chips. Most of the customers were in Asia, so I made several pre and post sales/support trips there as part of this role. I was very involved with the design team, as I was responsible for the methodology flow from synthesis forward, and provided feedback regarding design quality, area, timing, etc. In the second year, I was also responsible for overseeing our Unix IT consulting team and infrastructure.

Through SEI, I worked as an ASIC applications engineer for IBM Microelectronics. Supported several ASIC developments with numerous customers such as Apple, HP, Juniper, Ericsson (Germany), Silicon Graphics, etc., as their main technical liaison to IBM. I became an expert in the IBM ASIC tool flow including TestBench (LSSD), EinsTimer, etc. This position gave me the opportunity to see how several different companies designed their chips.

After completing my master's degree, I was accepted into an exchange program for professionals between Los Angeles and Berlin, funded by the German government. I worked for Bosch Telecom for the duration of the program.

As a Hughes Fellowship recipient, I worked full-time while simultaneously attending graduate school half-time at the University of Southern California on scholarship. Designed chips using LSI's tool flow and schematic capture, as well as truth tables + early day Synopsys synthesis.