Thevin Arokiaraj Lawrence

• Involved in the Integration of Memory subsystem block in the SoC and the mapping of functional and error interrupts from other blocks. • Solely responsible for performing block-level lint analysis to ensure code quality and compliance, thereby meeting strict milestone deadlines and contributing to the overall success of the Google SoC project.

• Served as the Single Point of Contact (SPOC) and lead for the System Peripheral block in a flagship Exynos processor chip, overseeing critical functions including haptic feedback, interrupt handling, I/O management via GPIO module, and thermal management. • Developed RTL logic with GEN Tcl file configuration, conducted comprehensive quality checks, and consistently met weekly block release deadlines.

• Designed the Read and Write channels between Peripheral and AXI interface with support for INCR burst type and burst size upto 3 for the design of AXI-4 Verification IP. • Reported directly to RTL design Director: Collaborated directly with the RTL Design Director, generated specialized Memory macros for the NVDLA AI subsystem, optimizing Area vs Speed trade-offs of SRAM and Register File macros using the ARM Artisan Memory Compiler.