Dipl.-Ing. Antonio Riobo

Angestellt, Senior FPGA and AI Engineer, Nomitri GmbH
berlin, Germany

Fähigkeiten und Kenntnisse

Electronic
engineer
vhdl
fpga
telecomunications
linux
communications
Software Development
FPGA
SoC
Nios II
Microblaze

Werdegang

Berufserfahrung von Antonio Riobo

  • Current 6 years and 5 months, since Jan 2020

    Senior FPGA and AI Engineer

    Nomitri GmbH

    Develop and simulate modules for FPGA using VHDL, Avalon IP Cores for Intel/Altera SoC device (HPS ARM processor) Modelsim Simulation, self-checking testbench. Tcl scripting. Trello for project management. Atlassian confluence documentation. Version managing with Git and bitbucket. Ubuntu OS.

  • 3 years and 7 months, Mar 2016 - Sep 2019

    Senior FPGA Software-Developer

    lla instruments GmbH

    FPGA Project Manager • FPGA aplications for the control of InGaAs sensors in NIR and RGB cameras. • FPGA aplications for the control of X-Ray Sensors,CCD and CMOS semiconductor sensors. • Comunication between FPGAs, CPLDs and uC. • Development using FPGA Communication Interfaces and data buses like ETH, SPI, RS232, I2C, LVDS, etc. • Synchronization of single ended signals between 4 FPGAs working in parallel. • Documentation • SVN projects with Tortoise, CollabNet • C++ with msys compiler

  • 7 months, Aug 2015 - Feb 2016

    ASIC-Developer for digital Circuits

    Robert Bosch Elektronik GmbH

    ASIC/FPGA consultant at CJ135 Project in Robert Bosch Fundation. • Software Design Top FPGA Model for ASIC Simulation with VHDL • Integration of VHDL-Module through GHDL scripting. Tcl scripting • Timing Constraining of very complex ASIC/VHDL Architecture Design, with a dozen PLL multiplexers. Timequest Quartus II • Modelsim Simulation, SystemC, OnBoard Verification mit SignalTap, Quartus II • Version management with DesignSync

  • 1 year and 1 month, Jul 2014 - Jul 2015

    FPGA Developer

    Siemens Healthineers

    VHDL Developing Engineer in Siemens Healthcare. • FLASH memory interfacing with SPI Flash, AXI Quad SPI master and slave VHDL interfaces. DDR2 Interface design. SiDaNet databus system. • Mentor Graphics development environment. Self-Checking test design using Modelsim SE-64 • Version management with SVN Tortoise.

  • 3 years and 5 months, Nov 2010 - Mar 2014

    FPGA-Developer

    Enasys GmbH

    Responsible for FPGA and microcontroller code development. Microblaze softprocessor design on Xilinx FPGA. Parallel and SPI ADC interfacing, Ethernet Interface, IIR Filter design. Simulation with ISIM and Modelsim. Timing optimization with several PLL modules. C programming for Microcontroller, Eclipse environment. Development of Labview application for user interface on RealTime Machine and development of Labview application for a remote IP data access. Version management with SVN Tortoise.

  • 3 months, Jun 2010 - Aug 2010

    Web developer

    Hostal Aqui

    I developed a complete new web site for the company

  • 3 months, Jun 2006 - Aug 2006

    IT department

    Teaxul S.A.

    Different projects of consulting, related with databases and embedded hardware

Ausbildung von Antonio Riobo

  • 10 months, Aug 2009 - May 2010

    electronic engineering

    Bellarmine University

    VHDL over FPGA implementation

  • 1 year, Sep 2007 - Aug 2008

    Telecomunications Engineering

    HTW des Saarlandes

  • elechtronic engineering

    Universidade de vigo

Sprachen

  • English

    C1 (Fließend)

  • German

    C1 (Fließend)

  • Portuguese

    C1 (Fließend)

  • Spanish

    C2 (Verhandlungssicher / Muttersprachlich)

  • Galicish first language

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