Asif Qaiyum

Technical lead of different IPs from concept to integration in SoC • Define IP specification with cross-functional teams • Explore design space (area, power, performance) of different architectures • Prototype IP for feasibility of the concept in Verilog/ Verilog-A/ MATLAB/Simulink Models • Design and verify transistor-level circuit implementation of mixed-signal IPs • Define DFT/trimming in the design to save test cost and for ease of test • Run Analog/Mixed Signal (AMS) simulation on chip level

• Study Circuit Implementations of the 1st integrator stage of a Continuous-Time Sigma-Delta Converter • Compare different operational amplifier / integrator topologies by analytical calculation and circuit simulation and identify the best topology with regard to power consumption and signal swing for the converter • Analyze and quantify the circuit characteristics and their spread considering non-ideal effects like noise, mismatch and process variations

Design Expertise • Developed IPs for Altera/Xilinx FPGAs • Architected fully pipelined architectures for maximum throughput • RTL development, Synthesis, STA and gate level simulation (GLS) • Scripting for debugging in development board (through digital testbus) Design and implement the following 1st pass FPGA based IPs • Tandem Free Operation (TFO) Egress • T1E1 line processor Soft Expertise • Managed team of 6 digital designers • Actively conducted hiring interviews

Expertise • Developed Advanced Encryption Standard (AES) Core for ASICs • Four silicon-proven IP flavors were implemented for different applications • Considered data path width from 32- to 128-bit • Architecture, RTL development, LINT checks • Synthesized in Synopsis and performed GLS and STA

• Implementation of AES in Assembly for TMS320C6711 DSP • Real-time data acquisition using Tern 586 engine board in C/C++

Communications Engineering (focus on Communication Electronics)

Computer Engineering