Atul Pandey

--Defined and implemented the read path architecture. Page-Buffer(sense amplifier) circuit design for 48nm MLC flash memory. --Mentored SRAM and Column decoder design --supported architecture definition and design of other analog blocks like Regulators, X-decoder, I/O (ONFI 1.0 spec compatible) and Charge pumps. --Involved in full chip simulation activity using HSIM and verifying firmware using verilog and SystemC and supported post silicon testing and characterization

--Worked on design of Register File circuits in 65 nm technology for a server class microprocessor. --Designed,ported and verified DDRII IOs to DDRII/DDRIII in the 65 nm technology. --Participated in the physical design of a complex block containing 250K gates using backend tools like DC, PC, Pathmill and Astro.

--Design of a Single Voltage Flash IP for use in Microcontrollers. --Designed Analog cells (Sense Amplifier,Charge pump, Power-On Reset ) --Wrote verilog model of IP (Array,pumps,read path) to be used for Microcontroller test bench and involved in post silicon debug and testing

--Designed a 8 bit 10MS/s Pipelined Analog to Digital Converter. Design included analog blocks like OTA, Sample and hold, comparator and sub ADC and DAC and layout supervision. --Digital error correction scheme incorporation.

worked on design of a 8bit, 10MS/s pipelined ADC