Eyal Brandstein

In my role, I'm responsible for all system level PCIe internal and external engineering activities, in order to achieve a successful product enablement & system integration of Qualcomm WiGig (802.11ad High-Speed WiFi) chipsets, within both Qualcomm-internal and customers platforms. In addition, I'm highly involved with post-Si development of WiGig data path (802.11ad Host MAC RX/TX).

ASIC Design SoC Engineer and PCIe Technical Lead for 40 GbE (Gigabit Ethernet) Controller (2011 - 2013); Product Enablement Engineer for 40GbE (2012 -2014) ; ASIC Design SoC Engineer (802.11 TX) for 100GbE Controller (2015 - 2016).

In this role within startup company, I'm technical design lead for PCIe Gen1 and Gen2 switch devices including Synopsys PCIe IPs integration, full chip SoC integration, DFT architecture & implementation, test program development, post silicon chip and system validation and customer technical support.

(1) SoC Integration for Power-PC based North-Bridge Chip (2) PCIe Post-Silicon Bring up lead for IBM North-Bridge Chip (3) Design-For-Debug (DFD) Logic Design/Verification for XBOX 360 Game Console's CPU & IBM North-Bridge Chip (4) Logic design for TCP/IP Offload engine IP.

Project: DVD & MPEG2 Encoder: (1) FPGA programming (Verilog) for DVD Chip Post-Si Validation (Interfaces Emulator) (2) Chip logic design of MPEG2 Encoder IFU (Interface Unit).

Graduated Cum Laude. Major in: computer networks; communication