Kalpitha Ramachandra

Processing of high speed Image on Line scan camera systems with 3 Clock domains. VHDL implementation of shading correction, pixel binning, X and Y Geometry correction and autocorrelation. Static timing analysis, Clock domain Crossing. CameraLink, SERDES, IOBUFS, DDR and Block RAM IP core implementation. Validation and Verification – Oscilloscope, Chipscope, Logic Analyzer debug. System and Functional verification. Assembling and Integration of hardware.