PRASHANTKUMAR JAIN

Angestellt, Design Verification Engineer, Mirafra Software Technologies Pvt. Ltd.
Gujarat, India, Indien

Fähigkeiten und Kenntnisse

Project Management
Team work
(Universal Verification Methodology)
| SystemVerilog
Constrained Random Verification
Functional Verification |
Assertion-Based Verification (ABV)
Functional & Code Coverage
Testbench Architecture & Development
Scoreboard & Monitor Implementation
Regression Testing & Debugging
Debugging & Root Cause Analysis
Verification Strategy & Execution
Time Management & Multitasking
Problem-Solving & Decision Making
Cross-Functional Collaboration
Languages & Methodologies
SystemVerilogUVM VerilogVHDL
Verification Techniques
Tools
Programming & Scripting
Domain Expertise

Werdegang

Berufserfahrung von PRASHANTKUMAR JAIN

  • Bis heute 1 Jahr und 6 Monate, seit Nov. 2024

    Design Verification Engineer

    Mirafra Software Technologies Pvt. Ltd.

    Project: I3C IP Verification | Client: Synopsys | Mar 2025 – May 2025  Analyze I3C/I2C specifications and define verification requirements for protocol compliance  Execute VIP-based simulations and validate features such as dynamic addressing and multi-controller support  Investigate waveform behavior and identify protocol-level issues  Contribute to functional validation of advanced serial communication interfaces

  • 1 Jahr und 1 Monat, Aug. 2023 - Aug. 2024

    Design Verification Engineer

    Boeing India Pvt Ltd

    Project: Tri-Mode Ethernet MAC & Data Mover IP Verification | Aug 2023 – Aug 2024  Develop detailed verification plans based on Ethernet MAC IP specifications  Design and implement directed and constrained-random test cases for data path validation  Integrate third-party VIPs and enable error injection mechanisms  Debug simulation failures and perform root cause analysis  Execute regression suites and drive functional coverage closure 

  • 8 Monate, Nov. 2022 - Juni 2023

    Design Verification Engineer

    Synapse Design

     Validate PHY IP for UCIe protocol using structured verification methodologies  Debug regression failures and resolve data path loopback issues  Analyze Analog Test Bus (ATB) failures and improve test coverage  Collaborate with design teams to ensure protocol compliance

  • 1 Jahr, Nov. 2021 - Okt. 2022

    Design Verification Engineer

    NXP Semiconductors

  • 1 Jahr und 3 Monate, Aug. 2020 - Okt. 2021

    Design Verification Engineer

    Sevitech Systems

    Project: MARS SoC Verification | Client: Nokia Siemens Networks | Aug 2020 – Jan 2021  Develop functional coverage models using Python-based automation  Perform code and functional coverage analysis for Bluetooth SoC  Debug failing test cases and improve test reliability

  • 1 Jahr und 1 Monat, Dez. 2016 - Dez. 2017

    Design Verification Engineer

    Guidsoft Technology (Client: BAE Systems)

    Design verification environment for ARINC-429 protocol-based systems  Implement test sequences, scoreboards, and predictors  Perform block-level and integration-level verification  Optimize functional coverage and validate aviation communication interfaces

Ausbildung von PRASHANTKUMAR JAIN

  • 3 Jahre und 10 Monate, Aug. 2006 - Mai 2010

    Bachelor of Technology in Electronics & Communication Engineering

    Gujarat University

  • 1 Jahr und 10 Monate, Sep. 2004 - Juni 2006

    Diploma in Electronics & Communication

    Technical Education Board, Gujarat

Sprachen

  • Englisch

    C1 (Fließend)

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