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Safi Majid

Student, MSc. Communications and Electronics Engineering, TU München

Skills

Electronics
Verilog VHDL
FPGA
Xilinx
Altium Designer
schematic design
Laboratory Testing and Validation

Timeline

Educational background for Safi Majid

  • Current 3 years and 1 month, since Oct 2023

    MSc. Communications and Electronics Engineering

    TU München

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