Vishwas Ravishankar

Bis 2024, Digital Verification Intern, STMicroelectronics
Grenoble, France

Skills

Verilog
Python
Cadence
Digital electronics
Verification
Digital Design
ASIC
Xilinx Vivado
Embedded Systems
SystemVerilog
Electronics
IC Design
Tcl
Cadence Xcelium
Cadence vManager
RTL Design
SoC Design
Team work
Communication skills
VHDL
FPGA Design
FPGA
Verilog Vhdl
MS Office
Microsoft Word
PowerPoint
Modelsim
Questasim
Adaptability
Problem Solving
Logical thinking
Analytical skills
Yosys
iverilog

Timeline

Professional experience for Vishwas Ravishankar

  • 7 months, Jun 2024 - Dec 2024

    Digital Verification Intern

    STMicroelectronics

  • 8 months, Feb 2023 - Sep 2023

    Research and Development Intern

    ABB

Educational background for Vishwas Ravishankar

  • 2 years and 1 month, Feb 2022 - Feb 2024

    VLSI Design and Embedded Systems

    R.V. College of Engineering

  • 2 years and 1 month, Feb 2022 - Feb 2024

    VLSI Design and Embedded Systems

    R.V. College of Engineering

  • 4 years and 4 months, Aug 2017 - Nov 2021

    Electrical and Electronics Engineering

    University Visvesvaraya College of Engineering

Languages

  • English

    First language

  • Hindi

    Fluent

  • Kannada

    First language

  • French

    Basic

  • German

    Basic

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